Renesas Electronics /R7FA6M3AH /SMPU /SMPUMBIU

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Interpret as SMPUMBIU

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)RPGRPA 0 (0)WPGRPA 0 (0)RPGRPB 0 (0)WPGRPB 0 (0)RPGRPC 0 (0)WPGRPC 0 (0)RPFLI 0 (0)WPFLI 0 (0)RPSRAMHS 0 (0)WPSRAMHS

WPGRPA=0, RPGRPB=0, WPGRPC=0, RPSRAMHS=0, RPGRPA=0, WPGRPB=0, WPSRAMHS=0, RPGRPC=0, WPFLI=0, RPFLI=0

Description

Access Control Register for MBIU

Fields

RPGRPA

Master Group A Read protection

0 (0): Memory protection for master group A reads disabled

1 (1): Memory protection for master group A reads enabled.

WPGRPA

Master Group A Write protection

0 (0): Memory protection for master group A writes disabled

1 (1): Memory protection for master group A writes enabled.

RPGRPB

Master Group B Read protection

0 (0): Memory protection for master group B reads disabled

1 (1): Memory protection for master group B reads enabled.

WPGRPB

Master Group B Write protection

0 (0): Memory protection for master group B writes disabled

1 (1): Memory protection for master group B writes enabled.

RPGRPC

Master Group C Read protection

0 (0): Memory protection for master group C reads disabled

1 (1): Memory protection for master group C reads enabled.

WPGRPC

Master Group C Write protection

0 (0): Memory protection for master group C writes disabled

1 (1): Memory protection for master group C writes enabled.

RPFLI

Code Flash Memory Read Protection

0 (0): Memory protection for code flash memory reads from master group A, B, and C disabled

1 (1): Memory protection for code flash memory reads from master group A, B, and C enabled.

WPFLI

Code Flash Memory Write Protection (Note: This bit is read as 1. The write value should be 1.)

0 (0): Setting prohibited

1 (1): Memory protection for code flash memory writes from master group A, B, and C enabled.

RPSRAMHS

SRAMHS Read Protection

0 (0): Memory protection for SRAMHS reads from master group A, B, and C disabled

1 (1): Memory protection for SRAMHS reads from master group A, B, and C enabled.

WPSRAMHS

SRAMHS Write Protection

0 (0): Memory protection for SRAMHS writes from master group A, B, and C disabled

1 (1): Memory protection for SRAMHS writes from master group A, B, and C enabled.

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